1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which reduces the number of pins for packaging.
2. Description of the Related Art
A semiconductor memory device is a device which can write data from an external portion and read the data again after a predetermined time. Signals related to the external portion include address signals for selecting a certain cell, command signals which control whether to read or write data, and data which is to be written/read to/from a certain cell. Typically, the signals are transmitted through separate pins.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 includes an internal circuit 1 a plurality of pins 2. The internal circuit 1 includes a register and control circuit 3, an address buffer 4, a DC generating circuit 5, a data buffer 6, a row decoder 7, a column decoder 8, and a memory cell array 9.
A plurality of pins 2 correspond to command signals RAS, CAS and WE, clock signals CK, address signals A[N:0], a power voltage VDD, a ground voltage VSS, and data DQ[M:0] to apply the signals applied externally and data to the internal circuit 1 and transmit the data to the external portion from the internal circuit 1.
The above components of FIG. 1 operate as follows in response to the command signals RAS, CAS and WE, the clock signals CK, the address signals A[N:0], the power voltage VDD, the ground voltage VSS, and the data DQ[M:0] which are applied through a plurality of pins 2.
The register and control circuit 2 receives and combines the external command signals CS, RAS, CAS, and WE which are transmitted through pins corresponding to the external command signals CS, RAS, CAS, and WE to determine operation status of the semiconductor memory device and generate control signals based on the determined operation status.
The address buffer 4 receives the address signals A[N:0] which are parallel-transmitted through pins corresponding to the address signals A[N:0] to generate a row address and a column address, and transmits the row address to the row decoder 7 and the column address to the column decoder 8.
The DC generating circuit 5 receives the power voltage VDD and the ground voltage VSS through pins corresponding to the power voltage VDD and the ground voltage VSS to generate voltages VPP, VBB, IVC, and VREF which are required by the semiconductor memory device.
The data buffer 6 is connected to pins corresponding to the data DQ[M:0], and applies data DQ[M:0], which are parallel-inputted, to the memory cell array 9 and parallel-outputs data DQ[M:0], which are parallel-inputted from the memory cell array 9, to pins corresponding to the data DQ[M:0].
The row decoder 7 receives the row address signals from the address buffer 4 to generate a word line selecting signal, and receives the column address signals from the address buffer 4 to generate a column selecting signal.
The memory cell array 9 writes/reads data to/from the memory cell array selected in response to the word line selecting signal and the column selecting signal.
As described above, the conventional semiconductor memory device has a plurality of pins respectively corresponding the signals and data, applies the transmitted signals to the internal circuit 1 to perform operations corresponding to the signals, and transmits data outputted from the internal circuit 1 to the external portion through a plurality of pins.
As the semiconductor memory device has more functions and achieves high integration, more signals and data are inputted and outputted, and thus the number of pins is increased to correspond to the increased signals and data.
In this case, however, integrating a lot of pins in a limited space causes many problems in packaging.
In addition, an electrical current consumed by the pins increases in proportion to the increased number of pins, leading to high power consumption.